1. Field of the Invention
The present invention relates to a bit line precharge signal generator for a memory device, and more particularly to a bit line precharge signal generator for a memory device which reduces a time delay occurring in a bit line.
2. Description of the Prior Art
As generally known in the art, a memory device such as a DRAM, SDRAM, or DDR DRAM transfers data stored in a memory cell to a bit line during a reading operation. A bit line sense amplifier senses and amplifies the data, transfers the data through a data line, and precharges a bit line. Then the memory device prepares a next operation.
In the same manner, the memory device transfers data to the bit line through a data bus during the writing operation. The bit line sense amplifier senses the data, stores it in the memory cell, and precharges the bit line. Then the memory device prepares the next operation.
At this time, a bit line precharge signal generator generates a signal for precharging the bit line.
FIG. 1A is a block diagram showing a path in which precharge signals blp, bleqd, and blequ generated by a conventional precharge signal generator 140 are applied to a plurality of bit line sense amplifier arrays 100, 110, 120, and 130.
As shown in FIG. 1A, the precharge signal generator 140 generates and outputs the precharge signals blp, bleqd, and blequ to the plurality of bit line sense amplifier arrays 100, 110, 120, and 130. Each of the bit line sense amplifier arrays 100 includes a plurality of bit line sense amplifiers. The signal blp denotes a bit line precharge signal, the signal bleqd denotes a bit line equalize down signal, and the signal blequ denotes a bit line equalize up signal. Memory cell arrays are located at both sides of the bit line sense amplifier. The signals bleqd and blequ are signals for controlling bit lines which are located at upper and lower memory cell arrays, respectively (FIG. 1C).
FIG. 1B is a circuitry diagram showing one example of the bit line precharge signal generator 140 shown in FIG. 1A. In FIG. 1B, an input signal bsx_u represents a signal which activates an output signal blequ.
FIG. 1C is a circuitry diagram showing one example of a conventional bit line sense amplifier. The bit line sense amplifier is included in the bit line sense amplifier array of FIG. 1A.
As shown in FIG. 1C, the bit line sense amplifier includes an amplifier, a first bit line equalizing transistor N1, first bit line isolation transistors N11 and N12, second bit line isolation transistors N21 and N22, a second bit line equalizing transistor N2, and bit line precharge transistors N3 and N4.
The first bit line equalizing transistor N1 is arranged at an upper portion of the amplifier. The first bit line isolation transistors N11 and N12 are arranged between the amplifier and the first bit line equalizing transistor N1. The second bit line isolation transistors N21 and N22 are arranged at a lower portion of the amplifier. The second bit line equalizing transistor N2 is arranged at the lower portion of the amplifier. The bit line precharge transistors N3 and N4 are arranged between the amplifier and the second bit line isolation transistors N21 and N22.
The first bit line equalizing transistor N1 is driven by the signal blequ. The second bit line equalizing transistor N2 is driven by the signal bleqd. The bit line precharge transistors N3 and N4 are driven by the signal blq.
In FIG. 1C, control signals C1 and C2 function to connect the bit lines BL and /BL to the amplifier. For example, during the reading operation, data of the the bit lines BL and /BL are transferred to a sense amplifier. The sense amplifier amplifies the data. During the writing operation, data transferred to the amplifier are transferred to the bit lines BL and /BL.
As described above, the signal blequ and the signal bleqd are signals for controlling bit lines which are located at upper and lower cell arrays.
When the signal blp of a high level is applied to the bit line sense amplifier, the voltage of the bit line in which the amplifier is located is equalized by a control voltage vblp.
The sense amplifier shown in FIG. 1C will be apparent to a person having ordinary skill in the art and having studied such a memory device, so description of details thereof will be omitted.
However, operations of the conventional bit line sense amplifier array and bit line precharge generator of FIGS. 1A and 1B have problems as follows.
(1) Since a plurality of bit line signals blp, bleqd, and blequ outputted from the bit line precharge signal generator are transferred to the bit line sense amplifier array, the signal line becomes longer, thus increasing a line resistance and causing difficulties for a layout.
(2) As known in prior art, referring to FIG. 1C, the bit line precharge signal blp, the bit line equalize down signal blequ, and the bit line equalize up signal blequ are applied to gates of the bit line precharge transistors N3 and N4, a gate of the second equalizing transistor N2, and a gate of the first equalizing transistor N1 to switch a bit line pair. The transistors functioning as switching means are located between the bit line pair. The bit line signals blp, bleqd, and blequ are applied to a gate of a corresponding transistor to turn on/off the corresponding transistor. When the transistors are turned on, the bit line pair are equalized at a constant voltage. In FIG. 1A, one bit line sense amplifier array includes a plurality of bit line sense amplifiers. Bit line signals are applied to corresponding transistors N1, N2, N3, and N4. However, since a capacitance component exists in gates of the transistors which receive the bit line signals, an RC time delay occurs due to a resistance component of a signal line of the bit line and the capacitance component existing in gates of the transistors which receive the bit line signals.
As shown in FIG. 1A, since a plurality of sense amplifier arrays are connected to each bit line signal in parallel, the capacitance component is increased to cause a significant RC time delay.
As stated previously, according to the conventional bit line precharge signal generator, (1) the signal line is long in order to increase the resistance component, and (2) since a plurality of bit line sense amplifier arrays are connected to the signal line in parallel, the capacitance component is increased, thus increasing a time delay during the applying of the bit line signal.